This invention relates to a bit pattern check circuit.
Generally, a bit pattern check circuit is used when transmitting bit information signals each comprising a plurality of bits for the purpose of checking whether each bit information is correctly sent with a predetermined bit pattern or not. In a known bit pattern check method, a plurality of check circuits of a number equal to that of the type of the predetermined patterns are prepared. With this method, however, the number of hardware elements increases with the number of patterns, thereby complicating the circuit construction. According to another method, a single memory device is used and bit information signals are applied to the address input terminals of the memory device. Thus a check is made as to whether a given bit pattern is correct or not by outputting pattern information signals stored in the memory addresses designated by the bit information signals. This method is advantageous in that the bit patterns can be checked with a single circuit even when the type of the pattern is large. With this method, however, as the bit information signals are supplied to the address input terminals of the memory device it is necessary to increase the address terminals of the memory device with the bit number, which increases the capacity of the memory device and makes it difficult to construct the same. For example, a typical data information utilized for data transmission is made up of 20 to 30 bits so that a memory device capable of receiving such bit information signal as an address information can not be available at present unless the memory device is manufactured by a special design requiring many difficulties.